Hardware-Level, Reverse-Engineering Resistant Logic Designs for Standard Complementary Metal-Oxide-Semiconductor (CMOS) Processes
This grant opportunity is focused on developing a hardware-based design for CMOS processes that enhances chip security by making them resistant to common attacks. In Phase I, the project requires outlining a hardware-level obfuscation strategy that resists reverse engineering through various methods and simulating its effectiveness on advanced nodes, like TSMC 28-nm or lower. The plan should a…
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